1. Technical Field
Embodiments of the present disclosure generally relate to a multi-channel self-refresh device, and more particularly to a technology relating to defects generated by a self-refresh operation of a multi-channel semiconductor device.
2. Related Art
A memory cell of a dynamic semiconductor memory such as a dynamic random access memory (DRAM) stores data within a capacitive element. Due to charges leaking from the capacitive element, the memory cell must be periodically refreshed. The refresh process performs the read operation for restoring a level of charges stored in the memory cell to an original state.
Different types of refresh methods have been developed. Generally, the auto refresh method is configured to use a refresh timer located outside of a memory chip, such that the memory chip can perform the refresh operation in response to a periodic refresh command from a controller. The self refresh method is configured to use a refresh timer located outside of the memory chip, such that all the memory chips are configured to request a refresh start command from the controller.
Typically, it is impossible for the refreshed memory cell to access the normal read and write operations. After the lapse of a predetermined time upon completion of one refresh operation, an active cycle may start an operation. In this case, the predetermined time is generally denoted by a refresh row cycle time (tRFC).
On the other hand, as the demand for higher-speed and higher-integration semiconductor memory devices is continuously increasing, the semiconductor memory devices have rapidly evolved into a multi-bank semiconductor memory device, a multi-chip semiconductor memory device, etc. in various ways.
Recently, the multi-channel semiconductor memory device has been proposed. The multi-channel semiconductor memory device provides a large bandwidth and is highly integrated. The multi-channel semiconductor memory device includes a plurality of memories in a single chip. Each memory includes an input/output (I/O) pad so that it can be operated as a separate memory device. That is, each memory of the multi-channel semiconductor memory device may operate as an independent memory device for independently inputting/outputting an address, a command, and/or data.
So that each channel can be independently operated, each channel for use in the multi-channel semiconductor memory device receives a command and an address separately from each other. For example, one channel performs refreshing, and at the same time the other channel performs writing. Therefore, respective banks allocated to each channel are sequentially refreshed at intervals of a predetermined time within the tRFC time.
A plurality of channels for use in the multi-channel semiconductor memory device may share one Temperature Compensated Self Refresh (TCSR) periodic pulse generator. The TCSR periodic pulse generator is a circuit to compensate for the self refresh period in response to a temperature.
However, although the multi-channel product is fabricated in a single chip, all channels contained in the multi-channel product can be operated independently from each other. Therefore, it is impossible for one TCSR periodic pulse generator to control two or more channels in the same manner as in “one-chip-one-channel product”.
In order to address the above-mentioned issues, if the TCSR periodic pulse generator is assigned to each channel, the area size and consumption current of each channel are unavoidably increased. In addition, all the TCSR periodic pulse generators must be targeted, resulting in an increased time consumed for product testing.
In addition, assuming that a self refresh command signal is asynchronously input to a plurality of channels, Pulse for Self Refresh (PSRF) may be enabled as soon as the self refresh command signal is input. In this case, one or more defective or failed cells may occur in a circuit operation of the refresh operation mode.